//////////////////////////////////////////////////////////////////////////////
// Filename:          /tp2/xima3s/xima3s23/Desktop/copro_final/new_xps/drivers/copro_final_v1_00_a/src/copro_final.h
// Version:           1.00.a
// Description:       copro_final Driver Header File
// Date:              Tue Jan 25 21:03:17 2011 (by Create and Import Peripheral Wizard)
//////////////////////////////////////////////////////////////////////////////

#ifndef COPRO_FINAL_H
#define COPRO_FINAL_H

/***************************** Include Files *******************************/

#include "xbasic_types.h"
#include "xstatus.h"
#include "xio.h"

/************************** Constant Definitions ***************************/


/**
 * User Logic Slave Space Offsets
 * -- SLAVE_REG0 : user logic slave module register 0
 * -- SLAVE_REG1 : user logic slave module register 1
 * -- SLAVE_REG2 : user logic slave module register 2
 * -- SLAVE_REG3 : user logic slave module register 3
 * -- SLAVE_REG4 : user logic slave module register 4
 * -- SLAVE_REG5 : user logic slave module register 5
 * -- SLAVE_REG6 : user logic slave module register 6
 * -- SLAVE_REG7 : user logic slave module register 7
 * -- SLAVE_REG8 : user logic slave module register 8
 * -- SLAVE_REG9 : user logic slave module register 9
 * -- SLAVE_REG10 : user logic slave module register 10
 * -- SLAVE_REG11 : user logic slave module register 11
 * -- SLAVE_REG12 : user logic slave module register 12
 */
#define COPRO_FINAL_USER_SLAVE_SPACE_OFFSET (0x00000000)
#define COPRO_FINAL_SLAVE_REG0_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000000)
#define COPRO_FINAL_SLAVE_REG1_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000004)
#define COPRO_FINAL_SLAVE_REG2_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000008)
#define COPRO_FINAL_SLAVE_REG3_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x0000000C)
#define COPRO_FINAL_SLAVE_REG4_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000010)
#define COPRO_FINAL_SLAVE_REG5_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000014)
#define COPRO_FINAL_SLAVE_REG6_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000018)
#define COPRO_FINAL_SLAVE_REG7_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x0000001C)
#define COPRO_FINAL_SLAVE_REG8_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000020)
#define COPRO_FINAL_SLAVE_REG9_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000024)
#define COPRO_FINAL_SLAVE_REG10_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000028)
#define COPRO_FINAL_SLAVE_REG11_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x0000002C)
#define COPRO_FINAL_SLAVE_REG12_OFFSET (COPRO_FINAL_USER_SLAVE_SPACE_OFFSET + 0x00000030)

/**
 * IPIF Interrupt Controller Space Offsets
 * -- INTR_DISR  : device (ipif) interrupt status register
 * -- INTR_DIPR  : device (ipif) interrupt pending register
 * -- INTR_DIER  : device (ipif) interrupt enable register
 * -- INTR_DIIR  : device (ipif) interrupt id (priority encoder) register
 * -- INTR_DGIER : device (ipif) global interrupt enable register
 * -- INTR_ISR   : ip (user logic) interrupt status register
 * -- INTR_IER   : ip (user logic) interrupt enable register
 */
#define COPRO_FINAL_IPIF_INTR_SPACE_OFFSET (0x00000100)
#define COPRO_FINAL_INTR_DISR_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x00000000)
#define COPRO_FINAL_INTR_DIPR_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x00000004)
#define COPRO_FINAL_INTR_DIER_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x00000008)
#define COPRO_FINAL_INTR_DIIR_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x00000018)
#define COPRO_FINAL_INTR_DGIER_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x0000001C)
#define COPRO_FINAL_INTR_ISR_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x00000020)
#define COPRO_FINAL_INTR_IER_OFFSET (COPRO_FINAL_IPIF_INTR_SPACE_OFFSET + 0x00000028)

/**
 * IPIF Interrupt Controller Masks
 * -- INTR_TERR_MASK : transaction error
 * -- INTR_DPTO_MASK : data phase time-out
 * -- INTR_IPIR_MASK : ip interrupt requeset
 * -- INTR_DMA0_MASK : dma channel 0 interrupt request
 * -- INTR_DMA1_MASK : dma channel 1 interrupt request
 * -- INTR_RFDL_MASK : read packet fifo deadlock interrupt request
 * -- INTR_WFDL_MASK : write packet fifo deadlock interrupt request
 * -- INTR_IID_MASK  : interrupt id
 * -- INTR_GIE_MASK  : global interrupt enable
 * -- INTR_NOPEND    : the DIPR has no pending interrupts
 */
#define INTR_TERR_MASK (0x00000001UL)
#define INTR_DPTO_MASK (0x00000002UL)
#define INTR_IPIR_MASK (0x00000004UL)
#define INTR_DMA0_MASK (0x00000008UL)
#define INTR_DMA1_MASK (0x00000010UL)
#define INTR_RFDL_MASK (0x00000020UL)
#define INTR_WFDL_MASK (0x00000040UL)
#define INTR_IID_MASK (0x000000FFUL)
#define INTR_GIE_MASK (0x80000000UL)
#define INTR_NOPEND (0x80)

/**************************** Type Definitions *****************************/


/***************** Macros (Inline Functions) Definitions *******************/

/**
 *
 * Write a value to a COPRO_FINAL register. A 32 bit write is performed.
 * If the component is implemented in a smaller width, only the least
 * significant data is written.
 *
 * @param   BaseAddress is the base address of the COPRO_FINAL device.
 * @param   RegOffset is the register offset from the base to write to.
 * @param   Data is the data written to the register.
 *
 * @return  None.
 *
 * @note
 * C-style signature:
 * 	void COPRO_FINAL_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
 *
 */
#define COPRO_FINAL_mWriteReg(BaseAddress, RegOffset, Data) \
 	XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))

/**
 *
 * Read a value from a COPRO_FINAL register. A 32 bit read is performed.
 * If the component is implemented in a smaller width, only the least
 * significant data is read from the register. The most significant data
 * will be read as 0.
 *
 * @param   BaseAddress is the base address of the COPRO_FINAL device.
 * @param   RegOffset is the register offset from the base to write to.
 *
 * @return  Data is the data from the register.
 *
 * @note
 * C-style signature:
 * 	Xuint32 COPRO_FINAL_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
 *
 */
#define COPRO_FINAL_mReadReg(BaseAddress, RegOffset) \
 	XIo_In32((BaseAddress) + (RegOffset))


/**
 *
 * Write/Read value to/from COPRO_FINAL user logic slave registers.
 *
 * @param   BaseAddress is the base address of the COPRO_FINAL device.
 * @param   Value is the data written to the register.
 *
 * @return  Data is the data from the user logic slave register.
 *
 * @note
 * C-style signature:
 * 	Xuint32 COPRO_FINAL_mReadSlaveRegn(Xuint32 BaseAddress)
 *
 */
#define COPRO_FINAL_mWriteSlaveReg0(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG0_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg1(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG1_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg2(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG2_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg3(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG3_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg4(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG4_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg5(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG5_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg6(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG6_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg7(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG7_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg8(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG8_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg9(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG9_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg10(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG10_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg11(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG11_OFFSET), (Xuint32)(Value))
#define COPRO_FINAL_mWriteSlaveReg12(BaseAddress, Value) \
 	XIo_Out32((BaseAddress) + (COPRO_FINAL_SLAVE_REG12_OFFSET), (Xuint32)(Value))

#define COPRO_FINAL_mReadSlaveReg0(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG0_OFFSET))
#define COPRO_FINAL_mReadSlaveReg1(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG1_OFFSET))
#define COPRO_FINAL_mReadSlaveReg2(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG2_OFFSET))
#define COPRO_FINAL_mReadSlaveReg3(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG3_OFFSET))
#define COPRO_FINAL_mReadSlaveReg4(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG4_OFFSET))
#define COPRO_FINAL_mReadSlaveReg5(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG5_OFFSET))
#define COPRO_FINAL_mReadSlaveReg6(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG6_OFFSET))
#define COPRO_FINAL_mReadSlaveReg7(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG7_OFFSET))
#define COPRO_FINAL_mReadSlaveReg8(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG8_OFFSET))
#define COPRO_FINAL_mReadSlaveReg9(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG9_OFFSET))
#define COPRO_FINAL_mReadSlaveReg10(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG10_OFFSET))
#define COPRO_FINAL_mReadSlaveReg11(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG11_OFFSET))
#define COPRO_FINAL_mReadSlaveReg12(BaseAddress) \
 	XIo_In32((BaseAddress) + (COPRO_FINAL_SLAVE_REG12_OFFSET))

/************************** Function Prototypes ****************************/


/**
 *
 * Enable all possible interrupts from COPRO_FINAL device.
 *
 * @param   baseaddr_p is the base address of the COPRO_FINAL device.
 *
 * @return  None.
 *
 * @note    None.
 *
 */
void COPRO_FINAL_EnableInterrupt(void * baseaddr_p);

/**
 *
 * Example interrupt controller handler.
 *
 * @param   baseaddr_p is the base address of the COPRO_FINAL device.
 *
 * @return  None.
 *
 * @note    None.
 *
 */
void COPRO_FINAL_Intr_DefaultHandler(void * baseaddr_p);

/**
 *
 * Run a self-test on the driver/device. Note this may be a destructive test if
 * resets of the device are performed.
 *
 * If the hardware system is not built correctly, this function may never
 * return to the caller.
 *
 * @param   baseaddr_p is the base address of the COPRO_FINAL instance to be worked on.
 *
 * @return
 *
 *    - XST_SUCCESS   if all self-test code passed
 *    - XST_FAILURE   if any self-test code failed
 *
 * @note    Caching must be turned off for this function to work.
 * @note    Self test may fail if data memory and device are not on the same bus.
 *
 */
XStatus COPRO_FINAL_SelfTest(void * baseaddr_p);

#endif // COPRO_FINAL_H
